I just ordered the De0-Nano-SoC and I am waiting for it to arrive. During my wait, I am trying to learn all I can about this device.
My initial goal will be to connect the device to my PC and transfer a data stream through the Ethernet port, over the HPS to FPGA bus and out through 8 GPIO pins at hopefully at a 10 GB/s rate or better. Are there any examples that are similar to my needs?
10 GHz over a 8bit parallel bus? I’m far from an expert but that sounds optimistic to me. Do you plan on using some kind of differential signaling or plain single ended? Will you also have a clock signal (which would have to run at 20GHz in this situation)?
Oops, I meant to type 6 MB/s on average. The GPIO needs to output up to 10MB/s at 60% width packets at about 45ms intervals. The De0-Nano-SoC device has a 1 Gigabit/s Ethernet.
Ah! that sounds more sane all of a sudden 
10MHz on the FPGA’s IO shouldn’t be much of an issue AFAIK, although you might run into difficulties depending on what you do with the parallel signal once it leaves the FPGA. If it doesn’t go very far on your PCB and you match your lines decently I think it shouldn’t be too difficult to make it work, however if you intend to go over long distances and/or a noisy environment it might get trickier. There’s a reason modern high speed interfaces are generally serial and differential!
10MB/s on gigabit ethernet should be relatively easy to achieve, however you might run into latency issues. What happens if there’s a delay on the network and your hardware FIFO starves? Is it a problem? Do you need a deep buffer to protect against that? Is there a limit to how much you can buffer, do you have latency constraints? The answer to these questions might orient your design.
I will try to give some numbers to start. The FPGA will output a clock of about 6MHz in groups of about 200 cycles. Call it 35us run time. During this clock time, the FPGA will be shifting a byte through 8 GPIO pins with each clock cycle to load an external register. My transfer distance will be about 20cm and several lines will be paired with grounds. After about 10us of idle time, the process will repeat with 200 of the next byte set from the Ethernet fifo buffer. Note that total time is 35 + 10 = 45 us. The external register will send a trigger pulse to the FPGA every 45us and expect more data on time. The FPGA-HPS must get a new packet ready to load and sent during this time. If all works well, I will tweak it to go faster. I would imagine that DDR3 as the holding buffer for the Ethernet would be fast enough. I need to load the register with up to several GBytes without an interruption.