Ah! that sounds more sane all of a sudden 
10MHz on the FPGA’s IO shouldn’t be much of an issue AFAIK, although you might run into difficulties depending on what you do with the parallel signal once it leaves the FPGA. If it doesn’t go very far on your PCB and you match your lines decently I think it shouldn’t be too difficult to make it work, however if you intend to go over long distances and/or a noisy environment it might get trickier. There’s a reason modern high speed interfaces are generally serial and differential!
10MB/s on gigabit ethernet should be relatively easy to achieve, however you might run into latency issues. What happens if there’s a delay on the network and your hardware FIFO starves? Is it a problem? Do you need a deep buffer to protect against that? Is there a limit to how much you can buffer, do you have latency constraints? The answer to these questions might orient your design.