Fail safe boot / Arria10 reconfiguration and SDRAM


#1

With C5 SOC we used a fail safe boot mechanism where u-boot based on its enviroment settings could choose between 2 sets of FPGA image, rootfs and kernel.

With the A10 the FPGA peripheral part has to be configured to be able to use the SDRAM from the HPS (early I/O init) The remaining RBF has to come from the same build as the RBF used for the peripherals. It seems theer is no other option than adding more intelligence into the SPL if we want to implement fail safe boot, or something as a Linux RAMDISK image to perform a system update.

Is it possible to do a full reconfiguration of the FPGA after the HPS is booted into the u-boot prompt without loosing the SDRAM ?

Any other options to get more flexibility ?