All,
I have a Cyclone V SoC development kit and would like to use the HPS to program the FPGA. By following the instructions in this link https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA, my .rbf image and SPL image is locate in QSPI on board.
quartus_hps -c 1 -o PV -a 0 preloader-mkpimage.bin
quartus_hps -c 1 -o PV -a 0x800000 ghrd_raw_bin_output.rbf
BSEL onboard is set to: J28(RIGHT), J29(LEFT), J30(LEFT)
MSEL is set to: 00000 (NO COMPRESSION, NO DESIGN SECURITY, FAST POR)
CSEL is set to: J26(RIGHT), J27(RIGHT)
I modified the socfpga_common.h according to link reference and #define CONFIG_SPL_FPGA_LOAD and #DEFINE CONFIG_SPL_FPGA_QSPI_ADDR (0x800000), rebuild the preloader and generated the binary file without error.
Programmed .bin and .rbf were success onto the QSPI, but after the cold reset or POR, and it tried to program the FPGA failed. Below is the error message displayed on the UART console:
FPGA: Programming FPGA
SF: Read data capture delay calibrated to 3 (0-7)
SF: Detected N25Q512 with page size 65536, total: 67108864
FPGA: Poll CD failed with error code -4
ERROR ### Please RESET the board
After searching around for error code -4, I find fpgamgr_program_poll_cd() reports back “FPGA: Timeout waiting for program” What does this mean? I am not sure if I am missing some settings or etc would cause it not to configure the FPGA correctly?