Hello i have a custom board and it has a CYCLONE V 5CSEBA5U23I7 on it.
on our custom board the HPS and the FPGA share the reset pin. both are getting the power on reset from the same source at the same time. e.g. when i switch on the FPGA boots from its own QSPI and the HPS loads the preloader from its own QSPI. both are power on independently.
i am not sure how to make the power on sequence.
the FPGA must need to boot first from the HPS if i am using H2F master and H2F lw bridge in the FPGA?
Here is what happens. when i power on my device i see that the H2F master and H2F lw bridges are not initialized automatically by the HPS. Although they exist in my QSYS project.
Then i manually initialize both bridges manually in the baremetal application in HPS firmware.
Now if i flash my program on the HPS and do a power on. the program on the HPS traps. and i think it traps because it does not see the H2F bridges.
but if i flash the *.sof on the FPGA and then start my HPS then every thing works perfect.
is there any one who can suggest me what should be the power on sequence required if i want to use the resources of the FPGA on the HPS?