I’ve spent some time trying to decipher Altera’s FPGA-to-HPS design. I’ve looked at Platform Designer, their IP verilog files, as well as read online documentation regarding the individual modules (images are below). What I do not understand is how/where the FPGA fabric has access to read data from the DDR memory (i.e. need an explanation of the Qsys DMA /Memory/FPGA connection in the image below) ? Looking at the generated IP verilog files, I can see that the DMA is connected to the L3 interconnect but at no point are any signals exported from the DMA_system module or the arria_10_hps module in Platform Designer to give the FPGA user access to read data. How does the FPGA send the appropriate signals to receive data from the DDR ?