FPGA to SDRAM - Cyclone V - Can write but cannot read

jakewong1992 · October 3, 2021, 4:02am

I finally got this working. It looks like the reason was indeed something to do with the HPS registers.

When using the HPS and adding some peripherals, we need to modify the registers and set some startup macros in the bootloader so that they are set in a correct order. This is explained for cyclone V devices at this link:

Unfortunately, the example seems to be for [cyclone V soc dev kit] (Cyclone V SoC Development Kit and SoC Embedded Design Suite) and doesn’t work for the de10-nano.

Also, I’m using debian and my own custom bootloader as explained on my tutorial at https://github.com/zangman/de10-nano/wiki. Perhaps that is also preventing this method from working.

After a lot of digging around, I found the following link which shows what registers need to be modified:

https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge

I used the following reference to get the addresses of the various registers mentioned in the article:

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1411577374877.html

So basically, when starting up I cancel autoboot at the beginning and enter the following commands:

Set fpgaportreset to 0x0:
```
 mw 0xFFC25080 0x0
```

Load a design that reads the sdram with the following comamnds:

fatload mmc 0:1 0x2000000 sdr.rbf
fpga load 0 0x2000000 0x700000

Set the apply bit of the staticcfg:
```
mw 0xFFC2505C 0xA
```
Re-enable fpgaportreset:
```
mw 0xFFC25080 0xFFFF
```
Continue booting:
```
boot
```

After this, the SDRAM read works as expected.

Best way to automate this is to create a boot script and enable u-boot to trigger this. I will share details on this step if I can get to documenting it.