GSRD Release Binaries not working on Arria 10 SD/MMC


#1

We have an Arria 10 SoC dev brd (p/n: 6XX-44382R-OM s/n: 10ASXSoC002854), which boots fine using the factory provided SD card (& FPGA image). However, attempts to replace the socfpga.rbf on the SD card with Released Binaries result in the following message “emif_reset interrupt acknowledged”, followed by a system reset and reloading of the FPGA, then ‘wash-rinse-repeat’.

I’ve tried all the Release Binaries for the Arria 10 SoC dev board: 17.1, 17.0 and 16.1. My method was to mount the SD/USB adapter to my dev Host, replace the factory image with the different version, reinstall on dev board, power-on an observe the terminal window for a successful boot sequence.

I’ve also tried rebuilding the GSRD design in 17.1, then loading the rbf on the SD, again without success.

Shouldn’t the Release Binaries just work?
Is the loaded bitstream verified somehow during u-boot?
Is there a version check performed? The stdout below suggests there’s a CRC checkout performed; on what?
Shouldn’t I be able to rebuild the GSRD design and load the bitstream?

'
U-Boot 2014.10 (May 01 2016 - 08:22:23)

CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
FPGA: writing socfpga.rbf
FPGA: Success.emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
Error: Could Not Calibrate SDRAM
DDRCAL: Failed
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe2db10
DRAM : 0 Bytes
WARNING: Caches not enabled
MMC: *** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Model: SOCFPGA Arria10 Dev Kit
Net: dwmac.ff800000
Error: dwmac.ff800000 address not set.

Hit any key to stop autoboot: 0
Early IO release is not enabled!!
** Unable to read file u-boot.scr **
Optional boot script not found. Continuing to boot normally
dwmci_send_cmd: DATA ERROR!
Error reading cluster
** Unable to read file zImage **
dwmci_send_cmd: Timeout.
** Can’t read partition table on 0:0 **
** Invalid partition 1 **
FPGA BRIDGES: enable
data abort
pc : [] lr : []
sp : ffe3bc90 ip : ffe21e6c fp : 00000000
r10: ffe222c0 r9 : ffe2e310 r8 : 00000000
r7 : ffe33ccc r6 : 00000003 r5 : ffe26c1c r4 : ffe26c1c
r3 : 016f2818 r2 : ffe3bcac r1 : ffe3bca8 r0 : 00008000
Flags: nZcv IRQs on FIQs off Mode SVC_32
Resetting CPU …