Hello all,
I am currently trying to write data (generated on the FPGA side) to the HPS via de f2h_sdram bridge. I want to do this because (from what I understand) it bypasses the L3 switch, which makes the data transfer faster.
I am using the DE10-Standard board, and I start with GHRD project for this board, which has the f2h_sdram bridge already enabled in Qsys (I change the data width to 32 instead of 256) and I export the bus so I can use it on my top level code. I followed the simple write criteria for avalon mm, which seems to be very simple. Essentially, I have 5 signals to send in: address, write, writedata, byteenable, and burstcount. I simply set the following constant values:
address = 30’h20000000, write = 1’b1, writedata = 32’h17, byteenable = 4’b1111, and burstcount = 8’d1
On the hps side I use:
busybox devmem 0x20000000
to read the contents of the address I am supposed to be writing to it but I never reads the value 17.
Moreover, I have checkd in my linux that bridge is enabled by checking the state of the bridge from /sys/class/fpga_bridge/br3 which is the f2h_sdram bridge.
Is there something fundamental that I am missing here?
Thank you for any help.
P.S. I have also tried making my own Qsys block with a master avalon mm interface with a very simple code but I still cannot write to the memory. The code is shown below.
`timescale 1 ps / 1 ps
module mem_write (
output logic [29:0] avm_m0_address,
input logic avm_m0_waitrequest,
output logic avm_m0_write,
output logic [31:0] avm_m0_writedata,
input logic clk,
input logic reset
);
reg [31:0] cnt;
assign avm_m0_address = 30’h20000000;
assign avm_m0_write = 1’b1;
assign avm_m0_writedata = {30’d0, cnt[26], cnt[25]};
always @(posedge clk) begin
cnt <= cnt + 1’b1;
end
endmodule
P.S.P.S
For those interested: Previously I was saving data to the On-chip ram of the fpga and then using a dma to transfer data to the hps via the axi bridge. I am generating data at 16MB/s and filling up a 128kB ram. Once the ram is 1/2 full i trigger the dma from the HPS side to transfer the data from the first half of the ram to HPS. While this is happening the fpga continues to write to the rest of the on-chip ram. Once I filled up a 32MB buffer on the HPS side I save it into a file. Nevertheless, the HPS overhead to save the file is too much (only sometimes) causing me to miss data. If I can write directly to HPS RAM without the HPS keeping track of the dma, I could use the HPS just for data saving, which would fix my problem.