High data rate transfer between FPGA and HPS

Hi everybody,

(First of all, sorry if something is missing in this post, it’s my first time posting here, give me feedback and I’ll follow your tips :slight_smile: )

So a little bit of context : I’m a beginner in SoC world. I am using a DE10-standard board from Terasic, and I’ve done a lot of tutorials from everywhere (Rocketboard, Terasic, Git projects etc…). I’ve also chosen to use the RsYocto project because of the ease of implementation and development. You may also need to know that I’m using Python scripts on the HPS.

At this point, I must explain my need : exchange data between HPS and FPGA in both directions (receive and send) at a data rate around 20 Mbits/s.

I’ve first tried to use only HPS2FPGA bridge by reading registers in the FPGA from the HPS (32 bits PIO register, FIFO connected to the AXI bridge). But in every design I’ve made, I wasn’t able to reach a speed of 20 Mbits/s. After this, I read a lot of topics about FPGA2HPS and F2SDRAM bridges, and I tried to implement a communication using the F2H bridge, which I didn’t succeed.

Therefore I would like to ask you, according to your experience in SoC designs, if it is possible to reach my need ? If yes, could you give me examples of architecture able to reach this need ?
Is it necessary to use F2H or F2SDRAM bridges ?
In this case, do I need to use DMAC or can I make a custom master in VHDL ?

(If you have any examples of F2H or F2SDRAM implementation using python I would be grateful to you)

Thanks a lot for your help, and your time.


The answer to your problem really depends on how you’re going to use the data in the HPS program side and the in FPGA logic.

If your 20Mbps is 1 bit that changes with a rate of 20MHz or it’s a byte/word or an array.

Usually high data rates transactions between the FPGA and the HPS are between memory spaces of the FPGA and the HPS (either by using dma or with custom master)

As a starting point I recommend that you use the HPS onchip ram as an address space that you can access from both systems

On the HPS side you can use this memory space similarly to using the h2flw bridge (opening dev/mem and using mmap to the corrects offset)

On the FPGA side you need to connect to the f2h bridge and read/write from the HPS ocr offset

You can use the dma soft IP with the csr connected to the h2flw bridge
You can also write your own master and it might be easier to control it either using a car like port that connects to the HPS or even using switches or buttons - depends on your application