I’m working with u-boot-socfpga-socfpga-2021.04_RC. I want this code to work because the upstream u-boot-2021.04 has much better support for NVMe and requires less patches for my code. I had it working minus ECC but was not able to get ECC working when I tried to bring the code forward from the socfpga version of u-boot.
Using an identical configuration (and slightly adjusted patches) on the release candidate of socfpga u-boot, compiling works but I’m running out of space in the SPL.
spl/u-boot-spl.bin exceeds file size limit:
limit: 0xf4f0 bytes
actual: 0xf52c bytes
excess: 0x3c bytes
I haven’t found any features I can remove to get more space.
I suspect they have added code for 10th generation SOCFPGA and have not selected it based on the target part which has caused the Cyclone V code to balloon beyond the 60 KiB maximum space available in the Cyclone V SPL.
I’m going to do what I can to dig in and disable code, but I’d like to report this to the developers at: GitHub - altera-opensource/u-boot-socfpga at socfpga_v2021.04_RC and I wasn’t able to find a mailing list or forum where they hang out.
Does anyone know where to get ahold of them?
Thanks in advance.
Update: I solved my problem by removing SPI drivers for parts not on my BOM. However, I’d still like to let the developers know about their size increase. This configuration used to fit.