How to read fifo buffer by the fpga on the SoC?

[Doug314]

I have the DEO NANO SoC. There are primarily three explained examples I can find.
HPS console output… which is trivial with the Atlas image.
HPS to FPGA to GPIOs… The transfer rate is regulated by the c code of the HPS
FPGA to GPIO… Same as above but using different input such as counter or buttons.

I have data at the HPS generated in packets. I need to put this data in a buffer and read it at a uniform rate with the FPGA.

Here is what I have to date:
I wrote some code that included Avalon FIFO memory in Qsys. I wrote a simple loop in c code to write 0 to 100 to the register with no delays. On the FPGA side, I have a 1 HZ clock pulse triggering it to read what I think is the fifo register value to transfer the low 4 bytes to an LED and watch it blink and “count”. My result is no blinking LEDS and no minute and a half of good results. Please help.

[lingljp]

@Doug314

I have the DEO NANO SoC. There are primarily three explained examples I can find.
HPS console output… which is trivial with the Atlas image.
HPS to FPGA to GPIOs… The transfer rate is regulated by the c code of the HPS
FPGA to GPIO… Same as above but using different input such as counter or buttons.

I have data at the HPS generated in packets. I need to put this data in a buffer and read it at a uniform rate with the FPGA.

Here is what I have to date:
I wrote some code that included Avalon FIFO memory in Qsys. I wrote a simple loop in c code to write 0 to 100 to the register with no delays. On the FPGA side, I have a 1 HZ clock pulse triggering it to read what I think is the fifo register value to transfer the low 4 bytes to an LED and watch it blink and “count”. My result is no blinking LEDS and no minute and a half of good results. Please help.

Maybe you want to add signaltap II and check the fifo timing, and figure out the reason why it can not be achieved.