I am a happy owner of the Atlas-SoC and I was succesfully implemented the design that provides an ADC data from FPGA to HPS via LW_HPS2FPGA bridge. Because the lightweight bridge waste a lot of adress spase (12 bytes from each 16!) I would like to replace it with 128 bit HPS2FPGA bridge.
I implemented my own Avalon MM module with 128 bit readdata bus, added it into Qsys project and tryed to access the data.
I based my C program on the example from System CD.
I am getting the address base:
virtual_base = mmap(NULL, HW_REGS_SPAN, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, HW_REGS_BASE);
Then I am trying to access my data by AXI:
h2p_adc_addr = virtual_base + ((unsigned long) (0xC0000000 + AVALON_ADC_0_BASE) & (unsigned long) (HW_REGS_MASK));
Then I am reading 4 32 bit words starting from h2p_adc_addr but all of they are zero instead of the expected data.
I was connected my component to the LW AXI bridge as well (it now connected to both HPS2FPGA bridges)
h2p_adc_addr = virtual_base + ((unsigned long) (ALT_LWFPGASLVS_OFST + AVALON_ADC_0_BASE) & (unsigned long) (HW_REGS_MASK));
and when I am reading the data from the LW AXI
I am getting the first word with 32 less significant bits of what I expected and four others with zeros instead my data. It shows that my Avalon module works actually.
So the questions are:
- Is it possible to use AXI bridge in GHRD on DE0-Nano-Soc?
- If yes - how I can access it?
- If no - how it’s possible to make full AXI available?
Thanks a lot in advance!