How to use SPIM1 from userspace(cyclone V)

I want to use SPI from userspace (linux), i have configured SPIM1 in Qsysy pin multiplexing.
But i cant see /dev/spidevX , how can i enable spi in linux to read write to my slave device from linux user space?

Are you running a GSRD Linux release?
Are you wanting to interface to the raw device driver or something like spidev?
Are you trying to interface to a memory device (flash or EEPROM)?

Here’s an attempt to impart some helpful info…

After enabling SPIM1 you’ll need to generate a new DTB from your QSYS project so Linux knows the device is present and enabled. Look again to see if something shows up either in /dev/ or in /sys/class as follows:

I’m running on Arria10 and SPIM1 shows up as “spi32766” here:

If I add a DTB binding to an EEPROM (as an example) then something will show up like:

If you add the spidev driver binding to the SPIM1 portion of your DTB then you should get something like:

Mine looks like:

Hope this helps a little.

FYI - If helpful

I had to enable the spidev driver and re-compile the Kernel.

My spidev DTS addtition looked something like:

		spi0: spidev@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <1000000>;
			enable-dma = <0x1>;

Complete example:

	spi@0xffda4000 {
		compatible = "snps,dw-spi-mmio-16.1", "snps,dw-spi-mmio", "snps,dw-apb-ssi";
		reg = <0xffda4000 0x100>;
		interrupt-parent = <0x3>;
		interrupts = <0x0 0x65 0x4>;
		clocks = <0x1d>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		bus-num = <0x0>;
		num-chipselect = <0x4>;
		status = "okay";

                    /* added by me */
		spi0: spidev@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <1000000>;
			enable-dma = <0x1>;

Thanks jhaberly,

I was trying to adopt the yacto envirnment , finally achive to build the device tree and kernal only.

I am trying to use another spi device from userspace program, so i need spidev device.

as per your guidance i have followed steps as below.

  1. I have first enable in kernel by menuconfig

Device Driver=>SPI Support=>User mode SPI device driver support <*>

2)then rebuild image and then

3)I have changed socfpga.dtsi from
spi0: spi@fff00000 {
compatible = “snps,dw-apb-ssi”;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
num-cs = <4>;
clocks = <&spi_m_clk>;
status = “disabled”;
spi0: spi@fff00000 {
compatible = “snps,dw-apb-ssi”;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
num-cs = <4>;
clocks = <&spi_m_clk>;
status = “okay”;
spidev0: spidev@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = < 100000000 >;
enable-dma = < 1 >;
4) then build the device tree
5)then generate fitimage
6)deployed on board

But there is no any spidev device under /dev or no any error msg in boot log for spi device.

did i forget something or anything wrong change ?

Did you update your preloader after the changes you made in Qsys ?

Yes i have copied hps_isw_handoff files to preloader and build preloader, then depployed preloader output to emmc of my board. But there is no any SPIdev port under /dev.

[ 3.000519] ### dt-test ### start of unittest - you will see error messages
[ 3.001365] OF: /testcase-data/phandle-tests/consumer-a: could not get #phandle-cells-missing for /testcase-data/phandle-tests/provider1
[ 3.001379] OF: /testcase-data/phandle-tests/consumer-a: could not get #phandle-cells-missing for /testcase-data/phandle-tests/provider1
[ 3.001402] OF: /testcase-data/phandle-tests/consumer-a: could not find phandle
[ 3.001422] OF: /testcase-data/phandle-tests/consumer-a: could not find phandle
[ 3.001442] OF: /testcase-data/phandle-tests/consumer-a: arguments longer than property
[ 3.001460] OF: /testcase-data/phandle-tests/consumer-a: arguments longer than property
[ 3.002839] irq: no irq domain found for /testcase-data/interrupts/intc0 !
[ 3.010299] OF: overlay: overlay_is_topmost: #5 clashes #6 @/testcase-data/overlay-node/test-bus/test-unittest8
[ 3.010304] OF: overlay: overlay #5 is not topmost
[ 3.018846] OF: resolver: overlay phandle fixup failed: -22
[ 3.018852] ### dt-test ### resolve ot phandles (ret=-22), 1
[ 3.018858] ### dt-test ### FAIL of_unittest_overlay_high_level():2231 Adding overlay ‘overlay’ failed
[ 3.019049] ### dt-test ### FAIL of_unittest_overlay_high_level():2234 Adding overlay ‘overlay_bad_phandle’ failed
[ 3.019055] ### dt-test ### end of unittest - 148 passed, 2 failed

I dont understand the error, is it related to my change in device tree for spidev (spi0 and spi1)?
How can i doignose this error?

I have recived my DE0-NANO-SOC board and with default mmc i test the spi is working fine.


I have followed everything at
for DE0-NANO-SOC board

after completing i have plug the mmc card and the result is there is no spidev node under /dev

i am confused whats wrong there? here must be spidev up for use from user spcae

I am using cyclone V, DE1 SOC (quartus lite 19.1), I am following this tutorial. I made changes to .qsys file of GHRD which i get from here for routing SPI over FPGA, every thing is good (no connection error, 0 error 0 warning) but when i try to generate .hdl it stops with some error.

i just want to do SPI communication using python in HPS running linux.

Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender
Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender
Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_001.sender
Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_001.sender
Info: button_pio: Starting RTL generation for module ‘soc_system_button_pio’
Info: button_pio: Generation command is [exec /home/pratik/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/common -I /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/altera_avalon_pio – /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/altera_avalon_pio/ --name=soc_system_button_pio --dir=/tmp/alt8625_3109179678941513487.dir/0002_button_pio_gen/ --quartus_dir=/home/pratik/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt8625_3109179678941513487.dir/0002_button_pio_gen// --do_build_sim=0 ]
Info: button_pio: Can’t locate Getopt/ in @INC (you may need to install the Getopt::Long module) (@INC contains: /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa /home/pratik/intelFPGA_lite/19.1/quartus/sopc_builder/bin /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/common /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/altera_avalon_pio /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/site_perl/5.28.1 /tools/perl/5.28.1/linux64/lib/5.28.1/x86_64-linux /tools/perl/5.28.1/linux64/lib/5.28.1) at /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/altera_avalon_pio/ line 18.
Info: button_pio: BEGIN failed–compilation aborted at /home/pratik/intelFPGA_lite/19.1/quartus/…/ip/altera/sopc_builder_ip/altera_avalon_pio/ line 18.
Info: button_pio: Done RTL generation for module ‘soc_system_button_pio’
Error: button_pio: Failed to find module soc_system_button_pio
Info: button_pio: “soc_system” instantiated altera_avalon_pio “button_pio”
Error: Generation stopped, 18 or more modules remaining
Info: soc_system: Done “soc_system” with 17 modules, 1 files
Error: qsys-generate failed with exit code 1: 2 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis

	hps_0_spim1: spi@0xfff01000 {
		compatible = "snps,dw-spi-mmio-16.1", "snps,dw-spi-mmio", "snps,dw-apb-ssi";
		reg = <0xfff01000 0x00000100>;
		interrupt-parent = <&hps_0_arm_gic_0>;
		interrupts = <0 155 4>;
		clocks = <&spi_m_clk>;
		#address-cells = <1>;	/* embeddedsw.dts.params.#address-cells type NUMBER */
		#size-cells = <0>;	/* embeddedsw.dts.params.#size-cells type NUMBER */
		bus-num = <0>;	/* embeddedsw.dts.params.bus-num type NUMBER */
		num-chipselect = <4>;	/* embeddedsw.dts.params.num-chipselect type NUMBER */
		status = "okay";	/* embeddedsw.dts.params.status type STRING */
		spidev1: spidev@0 {
			compatible = "rohm,dh2228fv";	/* appended from boardinfo */
			reg = <0>;	/* appended from boardinfo */
			spi-max-frequency = <100000000>;	/* appended from boardinfo */
			enable-dma = <1>;	/* appended from boardinfo */
		}; //

	}; //end spi@0xfff01000 (hps_0_spim1)