HPS DDR3 assigments

I have a prototype board that uses a DDR3 SDRAM (2 chips of 256Mx16) connected to HPS in Cyclone V device. The board has a error, bank pins BA[0] and BA[2] are swapped, i.e. pin HPS_BA[0] from HPS is connected to pin DDR_BA[2] pin HPS_BA[2] is connected to DDR_BA[0], pins for address bit [1] are connected correctly. Consequently SDRAM calibration was failed during u-boot preloader start. Is it the way to re-swap this outputs ? I hope there is the way to solve it, maybe by change declaration in u-boot sources or HPS system.



I am having same issue. Have you found out any solution?
I am using custom board taking reference from Arria 10 and callibrated DDR3 in place of DDR4 , do you know where do i need to make changes?


We had the same problem after checking with 12 MHz we see that the symbol of ddr and his ba0 ba1 ba2 are ordered in up side down ; but since we discovered it only after manufacturing and assembly we drilled a 0.3mm hole to cut the trace , and did the exchange. From upper pads. We also checked the source and tried to exchange definition of sequencer_defines.h without success . .