HPS I/O loan / CAN transceiver access

I’m trying to access to the CAN transceiver pins from FPGA logic, on my Cyclone V SoC Development Kit board. Searching on the web and on the RocketBoards community, I found out that the unique solution to get it is to use the HPS I/O loan and that I also need the associated Preloader. Therefore I’ve downloaded the GSRD release 17.1 (for the Cyclone V) and, following the related guides, I’ve been able to create the SD card image and to run the GSRD on the board. If I’m not wrong, I can still preserve the GSRD basic flow (i.e. update the SD card and let it occupy of the whole duty work: boot with preloader included, FPGA programming, Linux distro boot, et al.). The only steps I must perform after modifications are:

  • generation of the Device Tree Blob file (.dtb) and replacement of the old .dtb file on the SD card;
  • generation of the RAW Binary File (for the FPGA programming) and replacement of the old .rbf file on the SD card;
  • generation of the new Preloader image (by means of the BSP-editor) and update of old Preloader by means of the related command (dd if=preloader-mkpimage.bin of=/dev/${sd_name}3 bs=64k seek=0).

I made a couple of tries, and “my flow” worked. Anyway I still not able to get my goal.
I changed the Uart Controller set in the hps_0 instance in Qsys (I set the HPS I/O Set 1 with no Flow Control for the UART0 controller), I set the CAN0 Controllers as unused and the I set the pin CAN0_RX and CAN0_TX as LOAN. Then I connected the related LOAN I/O to the ghrd top-level (as inout port) and the related h2f_loan_io, …_loan_oe and …_loan_out to my internal FPGA logic, as required for my project. The result is that I have not control over the CAN transceiver (I linked the TX pin to an FPGA push button to test it, after the removal of the PIO peripheral related to the FPGA push buttons) and I’ve lost the serial communication by means of the UART peripherals.
The serial communication is not needed for my project: in case I could preserve it it could an additional and useful features to see the GSRD boot flow and anything else. But I really need to connect to the CAN transceiver pins from the FPGA logic, with or without the GSRD SoC.

Can someone help me?

Hello Crocs,

Were you able to get the CAN communication running ? I am trying to communicate between Cyclone V SoC board and DE0 Nano board via CAN bus. However, DE0 Nano does not have the CAN controller connected directly to the pins, so I need to route these via the FPGA pins. I am working on CAN for the first time, and am stuck on how to proceed. Can you share some guidelines or tips on how to proceed with the CAN on cyclone V board and DE0 Nano? :slight_smile:

Hello soc_learner,

Yes I did it! I have been able to access the CAN Transceiver (not CAN Controller) pins from internal FPGA logic. Basically I used the HPS I/O Loaner, as specified by several tutorials and guides, but with some modifications. I started from the GHRD architecture and, by means of Qsys, I modified the SoC deleting all unused logic and changing the HPS I/O usage: I left unmodified the settings related to the UART controller, while I set all the settings related to the two CAN Controllers (the Cyclone V SoC provides 2 CAN Controllers) to ‘Unused’. Finally I set the UART_0 pins as Loan I/O: this because, at least in my case, the UART_0 pins are multifunction pins and they provide access also to the CAN Transceiver pins.
Then I simply followed the GSRD modification flow in case of boot from SD (and FPGA programming at boot time): I have generated the .sof (Quartus Assembler) and the .sopcinfo (Qsys), obtaining respectively the .rbf and .dtb file, and then I generated the update preloader image. Finally I replaced the SD card content with the files just mentioned and everything worked. The FPGA is programmed at boot time (from the SD card) and I am able to access the CAN controller pins directly from the FPGA logic.

As specified more time, I am referring to the CAN Transceiver pins; if your goals is to access the CAN Controller pins directly from the FPGA, you just have to select the FPGA option in the section of the HPS that is related to the two CAN Controllers.

I hope to have been helpful. If you need more details, just ask :smiley:

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Trying to decipher the difference between FPGA and HPS I/O Set (0/1)…which I think your post alludes too…