IP Core as Hardware Accelerator with HPS in DE1-SoC

Hi all,

I am interested on implementing a Hardware Accelerator running on FPGA, with access via Software running on HPS (ARM). I am using DE1-SoC. After doing that, I am failing on reading any data from my IP Core. I am not sure if is a problem from my IP Core code, or address mapping, or even if I am doing something wrong with Qsys.

Anyone has something about that to share? Maybe a tutorial, example, anything?

Thank you in advance!