Kernel Freezing on Boot - fpga/hps bridge broken

Hey guys!

I have a design which contains some logic that uses the fpga to hps bridge, as all as interruption from fpga to the hps. The thing is that I have updated the “Device Tree Blob” to add the interruption capability (the last feature I added to my design). Previously my design did work correctly, and I could send data to the SDRAM with the FPGA.

Below is shown the boot procedure and my Qsys project. Do you

It seems that the hps2fpga_bridge breaks the boot process… This can be checked in the image below:

And we can see the cpu stalls.

And below is shown my Qsys design.

Does anyone know why this problem is being caused or knows how to debug this? If I replace my current .dtb to the one from my previous design the board runs correctly, so the Device Tree breaks everything up? I’m generating the .dtb through SoC EDS although when I run the command it says to me the modules for DMA Write Master and mSGDMA Dispatcher are unknowns… (Altera website says this warning can be ignored…).

The section that describes the sgdma dispatcher is shown below: (part of dtb)
modular_sgdma_dispatcher: unknown@0x100000000 { compatible = "unknown,unknown-15.0"; reg = <0x00000001 0x00000000 0x00000020>, <0x00000001 0x00000020 0x00000010>; reg-names = "CSR", "Descriptor_Slave"; interrupt-parent = <&hps_0_arm_gic_0>; interrupts = <0 41 4>; clocks = <&clk_0>; }; //end unknown@0x100000000 (modular_sgdma_dispatcher)

Thanks in advance!!

The error -22 with the bridges I got too yesterday with the GHRD and kernel 4.0.0. It seems that the devicetree generated by Quartus 15.1 lacks this rstmgr entry (see )and then the bridges and GMAC don’t work anymore and it crashes later in the boot process. I took the original DTB file from the GHRD and decompiled it to DTS (on a linux machine using the device-tree-compiler). I merged my changes and converted it back to DTB with the same tool. That worked for me regarding I2C1.

Maybe give it a try.

I did the same thing. I modified the original DTB by converting to DTS and adding the FPGA hardware info by hand.