L2 cache not compatible with AXI protocol?

I’m building a custom Linux image to use with my Altera Cyclone V board and I noticed the cache AUX_CTRL register from my Yocto build is different from the provided prebuilt image; I am wondering if these might be causing some issues (I discussed some things here).

The prebuilt image has a value of AUX_CTRL 0x32460000 and my build has AUX_CTRL 0x76460001 with the following boot messages:

[    0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C: platform provided aux values permit register corruption.
[    0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 ID prefetch enabled, offset 1 lines
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB

I looked in the ARM manual and found three bits which are now high or 1 in my build:

bit[0] - Full Line of Zero Enable

When the L2C-310 AXI slave ports receive a write transaction with AWUSERSx[10], it
indicates that the write actually targets a whole cache line and that all data of this cache line must
be reset to zero. The Cortex-A9 processor is likely to use this feature when a CPU is executing
a memset routine to initialise a particular memory area. When the L2C-310 receives such a write
transaction it ignores the AXI attributes attached to the transaction, size, length, data, and
strobes for example, because the whole cache line must be reset. This behavior is not compatible
with the AXI protocol, it is disabled by default. You can enable it by setting the Full Line of Zero
Enable bit of the Auxiliary Control Register, bit[0]. This behavior also relies on an enable bit in
the Cortex-A9 processor. You must take care if you enable this feature because correct behavior
relies on consistent enabling in both the Cortex-A9 processor and the L2C-310.

bit[26] - Non-secure lockdown enable
Non-secure accesses can write to the lockdown registers.


Early write response
The AXI protocol specifies that the write response can only be sent back to an AXI master when
the last write data has been accepted. This optimization enables the L2C-310 to send the write
response of certain write transactions as soon as the store buffer accepts the write address. This
behavior is not compatible with the AXI protocol and is disabled by default. You enable this
optimization by setting HIGH the Early BRESP enable bit in the Auxiliary Control Register,
bit[30]. The L2C-310 slave ports then send an early write response only if the input signal
AWUSERSx[11] (where x=0 or 1) is set to 1 for the corresponding write transaction.

Would any of these cause poor performance or delays? I am most suspect of the last change as it states

not compatible with the AXI protocol and is disabled by default