I’ve created a project on Platform Designer, from Quartus Prime Standard 17.1, using the Cyclone V HPS, and adding the Altera 16550 IP module. I have compiled the system, created .rbf and .dtb files based on this project.
I have checked that in the .dts file the correct “compatible” and "status = “okay” " lines are present. I have enabled in the kernel menuconfig the right flags to allow it to recognize the UART (Serial Port on open firmware platform bus, max number of altera UARTs…).
But still I only get two devices, ttyS0 and ttyS1, that are the UARTs provided by the HPS, not the FPGA Fabric Altera’s UART.
Has anyone encountered the same issue? Or could anyone please describe the full working flow to see if I am missing something?
Thank you in advance.