I am using cyclone V, DE1 SOC (quartus lite 19.1), I am following this tutorial. I made changes to .qsys file of GHRD which i get from here for routing SPI over FPGA, every thing is good (no connection error, 0 error 0 warning) but when i try to generate .hdl it stops with some error.
i just want to do SPI communication using python in HPS running linux.
log
Info: button_pio: Done RTL generation for module ‘soc_system_button_pio’
Error: button_pio: Failed to find module soc_system_button_pio
Info: button_pio: “soc_system” instantiated altera_avalon_pio “button_pio”
Error: Generation stopped, 18 or more modules remaining
Info: soc_system: Done “soc_system” with 17 modules, 1 files
Error: qsys-generate failed with exit code 1: 2 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis