Board: Altera Cyclone V SocFPGA
Quartus Lite 21.1
Embedded Design Suite Version 20.1 [Build 711]
linux-socfpga 4.20.8 transition to 5.15.80 LTS / 5.19
I have the following section in one of my overlay(s):
ad7173@0 {
compatible = “adi,ad7173-8”;
reg = <0>;
spi-cpol;
spi-cpha;
spi-max-frequency = <12500000>;
interrupt-parent = <&hps_0_gpio2_porta>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
miso-gpios = <&hps_0_gpio2_porta 4 GPIO_ACTIVE_HIGH>;
The interrupt parent hps_0_gpio2_porta being defined as:
hps_0_gpio2: gpio@0xff70a000 {
compatible = “snps,dw-apb-gpio”, “snps,dw-gpio-21.1”, “snps,dw-gpio”;
reg = <0xff70a000 0x00000100>;
interrupt-parent = <&hps_0_arm_gic_0>;
interrupts = <0 166 4>;
clocks = <&l4_mp_clk>;
#gpio-cells = <2>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
hps_0_gpio2_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 166 4>;
interrupt-parent = <&hps_0_arm_gic_0>;
gpio-line-names =
"HPS_GPIO_58", "HPS_GPIO_59",
"HPS_GPIO_60", "HPS_GPIO_61",
"HPS_GPIO_62", "HPS_GPIO_63",
"HPS_GPIO_64", "HPS_GPIO_65",
"HPS_GPIO_66", "HPS_GPIO_67",
"HPS_GPIO_68", "HPS_GPIO_69",
"HPS_GPIO_70", "HPS_GPIO_71",
"HPS_GPIO_72", "HPS_GPIO_73",
"HPS_GPIO_74", "HPS_GPIO_75",
"HPS_GPIO_76", "HPS_GPIO_77",
"HPS_GPIO_78", "HPS_GPIO_79",
"HPS_GPIO_80", "HPS_GPIO_81",
"HPS_GPIO_82", "HPS_GPIO_83",
"HPS_GPIO_84";
}; //end gpio-controller@0 (hps_0_gpio2_porta)
}; //end gpio@0xff70a000 (hps_0_gpio2)
I observe that the miso-gpio for the ad7173 triggers ONLY ONCE and then never again - even if enable_irq() is called.
Now; this was working in the 4.20.8 kernel but there we had the following path in-use to ensure that the MASK-register is also cleared in dwapb_irq_enable():
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index 6730c66…e42e3d0 100644
— a/drivers/gpio/gpio-dwapb.c
+++ b/drivers/gpio/gpio-dwapb.c
@@ -205,6 +205,8 @@ static void dwapb_irq_enable(struct irq_data *d)
u32 val;
spin_lock_irqsave(&gc->bgpio_lock, flags);
- /* Make sure MASK register is also cleared */
- irq_gc_mask_clr_bit(d);
val = dwapb_read(gpio, GPIO_INTEN);
val |= BIT(d->hwirq);
dwapb_write(gpio, GPIO_INTEN, val);
The function irq_gc_mask_clr_bit() is located in
kernel/irq/Makefile:obj-$(CONFIG_GENERIC_IRQ_CHIP) += generic-chip.o
and CONFIG_GENERIC_IRQ_CHIP is no longer defined (or should be necessary) for our standard platform which is
CONFIG_ARCH_INTEL_SOCFPGA=y
So my question goes; has anyone experienced the same issue with missing trigger of miso-gpios enabled GPIO IRQ(s), and if yes - how did you resolve it for the 5.x linux-socfpga?
Thanks.