MitySOM 5CSX-H6-53B-RC board stuck at initializing SDRAM ECC

Boot
1

Hello

We are having problems getting our firmware to boot in the MitySOM 5CSX-H6-53B-RC board. The firmware boots fine on the MitySOM 5CSX-H6-42A-RC board, but on the 53B board we get the following on boot before it gets stuck at initializing SDRAM ECC.

U-Boot SPL 2013.01.01 (Jun 14 2022 - 17:41:06)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 2048 MiB
SDRAM: Initializing SDRAM ECC

U-Boot SPL 2013.01.01 (Jun 14 2022 - 17:41:06)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 2048 MiB
SDRAM: Initializing SDRAM ECC

U-Boot SPL 2013.01.01 (Jun 14 2022 - 17:41:06)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 2048 MiB
SDRAM: Initializing SDRAM ECC

U-Boot SPL 2013.01.01 (Jun 14 2022 - 17:41:06)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 2048 MiB
SDRAM: Initializing SDRAM ECC

We are using the Yocto 4.9.78-ltsi build and have made the following changes to the firmware from the working version for the 42A board:

  • Changed hps row address width from 15 to 16 in qsys.
  • Verilog file has the array for the hps address extended to [15:0].
  • Added the extra IO_STANDARD, OUTPUT_TERMINATION, and PACKAGE_SKEW_COMPENSATION lines for the hps address in the qsf file, which gets assigned PIN_F24 when built.
  • Updated memory and qspi in dts files.
  • Tried with SDRAM_SCRUBBING enabled in bsp-editor.

We have tried the sample image from the Critical Link site for the 53B board and that boots fine.
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki#Variant-Specific

Any ideas of how to solve this issue? Might there be a change that Iā€™m missing?
Thanks.

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