Nios II debug over Ethernet/Remote System Debug


I am wondering if someone already is using the Remote System Debug over Ethernet to Debug a Nios II implemented in the FPGA Part of an Altera SoC and if this is even possible?

According to the following two documents, it should be possible to use the Ethernet Connection from the HPS (ARM) with a Linux Application, a generated Linux Device Tree and a SLD (System Level Debug) HUB Controller on the FPGA to replace the USB Blaster for SignalTap.
A SignalTap then would act as a SLD Node in my opinion.

But what’s about a Nios II as SLD Node?
In the documentation below they are just writing that the Nios II could be used instead of the HPS (ARM) to implement the network stack.

Thanks for your opinion, ideas and help



Main documentation:

Additional documentation: