PCIe root port example questions

RocketBoards General
1

Hi All,

we are developing Cyclone-V SoC based board, which will make use of 2 PCIe root ports (each having dedicated SATA controller on another end).

So far, we are investigating “PCIe Root Port” example (simple one, without SGDMA) and have some general questions about it. From the example, we can learn how the system is designed, but not why (which would be very nice to know when adapting example to our needs).

It would be very nice if someone could shed some more light on this matter, any comment would be greatly appreciated.

Questions we have so far:

  1. An example uses “external” SGDMA core, despite HPS has its own DMA controller (DMA-330).
    Are there any reasons for preferrering SGDMA over DMA-330?

  2. Is on-chip RAM used for illustration/testing purposes only or is it a must for PCIe to work?

  3. On the PCIe->MSI->GIC path, there is a “pb_rxm_2_msi” Avalon-MM bridge, which is clocked by PCIe.coreclockout clock. It feeds data directly into msi_to_gic_gen_0 (vector_slave port), which is clocked by HPS peripherial clock (clock50).
    Why is Clock-Crossing bridge not needed there?

  4. The “pcie_rp_ed_5csxfc6_board_info.xml” creates “pcie_rpde” node in DTS (compatible=“altr,pcie-rpde”). What is it?

  5. The “hps_clock_info.xml” seems to enumerate a lot of clocks. Why is it necessary? Doesn’t sopc2dts generate clocks based on .sopcinfo?

Thanks in advance,
Anatoly

2

For people who find this thread let me answer based on what I know:

  1. The altera default pcie driver does not use SGDMA. It does not use the SRAM. You can safely delete them, they are not needed and IMO are a waste of space.
  2. No it is not used.
  3. The software adds a clock crossing bridge for you. If you hover over the connection you will see a red dot and a note that it will add a clock crossing adapter for you.
  4. Custom logic that is not needed anymore. There is a better example from 2018 that is linked in rocketboards that does not have any local rtl: https://releases.rocketboards.org/release/2015.10/pcie-ed/hw/ There is a simple and full example there, but IMO they are both way overly complicated. Once I get my implementation working I will strip my code out of it and post a usable qsys file that is 2020.2 compatible.
  5. Don’t mess with the clocks. Just add your own pll and other clocks. Note about sopc2dts: it is very out of date. It crashed when I ran it on my Cyclone V design. I had to patch it to get it to stop crashing. Those patches are posted somewhere. I think on the sopc2dts git repo.