we are developing Cyclone-V SoC based board, which will make use of 2 PCIe root ports (each having dedicated SATA controller on another end).
So far, we are investigating “PCIe Root Port” example (simple one, without SGDMA) and have some general questions about it. From the example, we can learn how the system is designed, but not why (which would be very nice to know when adapting example to our needs).
It would be very nice if someone could shed some more light on this matter, any comment would be greatly appreciated.
Questions we have so far:
An example uses “external” SGDMA core, despite HPS has its own DMA controller (DMA-330).
Are there any reasons for preferrering SGDMA over DMA-330?
Is on-chip RAM used for illustration/testing purposes only or is it a must for PCIe to work?
On the PCIe->MSI->GIC path, there is a “pb_rxm_2_msi” Avalon-MM bridge, which is clocked by PCIe.coreclockout clock. It feeds data directly into msi_to_gic_gen_0 (vector_slave port), which is clocked by HPS peripherial clock (clock50).
Why is Clock-Crossing bridge not needed there?
The “pcie_rp_ed_5csxfc6_board_info.xml” creates “pcie_rpde” node in DTS (compatible=“altr,pcie-rpde”). What is it?
The “hps_clock_info.xml” seems to enumerate a lot of clocks. Why is it necessary? Doesn’t sopc2dts generate clocks based on .sopcinfo?
Thanks in advance,