Platform Designer (Qsys) DMA Slave Address


I’ve connected a DMA to manage the write and read operations between the FPGA and HPS using the FPGA-to-HPS SDRAM interface (image 1 below) found on the HPS. Does anyone know what the dma_ctl_address represents and why its only 3 bits (image 2 below) ? I’ve looked through the generated verilog ip files as well as gone through the online documentation, but found no explanation of this 3 bit addressing scheme. Does anyone know what this address refers to if I want the DMA to handle the communication with the f2sdram0 port from the FPGA ?

Also I should mention I am fairly new to Quartus, Qsys, etc and as such I may have this setup very incorrectly (the base template for this project works/tested). In this situation please let me know if I am using the DMA incorrectly.

Image 1:

Image 2:


The ctl bus is to access the internal registers of the DMAC and configure source and destiny size of the transfer, and to start the transfer. It is 3 because peripherals define their address bus size with the minimum needed. Internally the DMAC will have 2^3 registers at max in the documentation.
The data bus is 32bit(4B=2^2B). Therefore the number 2^3*2^2=2^5=32 byte address.
Connect the control bus to some HPS-FPGA master to be able to control the DMAC from the processor.