PLL inputs and outputs in Cyclone V device


I am trying to use the PLL to synthesize higher frequencies for my logic in FPGA. I am confused about the connections made to the PLL refclk and the outclock from the PLL.

Which pin needs to be connected to the refclk and how do I connect the PLL outclk to my logic?

Board: Arrow SoCkit
Cyclone V

Thanks for all your help.

I has been facing the same problem. All of the literature contain nice and simple node names, but any of them could be used in (current version) of Quartus Prime.
I have tried to do many experiments but I am still not sure about the proper solution.
By the way, as far as You would like to get know the necesary node names for timing constains into SDC files, the best way is to use derive_ppl_clocks command (eg. in a copy of Your SDC file or from TLC command line in TimeQuest) and observe sources and targets of derived clocks in TimeQuest Clock report or Clock Tree report. This is the most universial manner of getting the information for any setup of PLL IP core. Then You will be able to write down the right names to commands in Yours SDC files.
Please, do not panic, the node names are quite complicated and, moreover, some clocks are diverd inside the PLL! A good strategy is also to look at Technology Map Viewer to the instance of PLL compoment.
I hope this message help You a bit. Best wishes.
Jan Konečný.

My_first_fpga project tutorial in DE1-SoC board implements a PLL using schematic you can take a look to it.
ref_clk is the input clock. You have to connect it to the pin where the board manufacturer placed a clock input. If you use the Quartus Settings File .qsf for the golden reference design of the board you have the pins assigned and you can connect ref_clk to CLOCK_50 (this is the common name in terasic boards). The outclock is the output clock, you connect it to the clock pin in your schematics. If you are programming verilog you connect it to the always() loops. In VHDL if rising_edge(out_clk) then…

Hope it helps