Probelm with SPI MISO


I’d like to use the SPI master of Cyclone V HPS by routing it to the FPGA.
In the platform designer, I have set the SPIM0 to FPGA and connected the corresponding pins in the top level HDL.
I have added the following entry to the Linux devicetree:

     status = "okay";
     #address-cells = <0x1>;
     #size-cells = <0x0>;
     num-cs = <0x4>;
     spidev@fff00000 {
         compatible = "custom,spidev";
         reg = <0x0>;
         spi-max-frequency = <500000>;
         enable-dma = <0x1>;

Transferring bytes to a verilog SPI slave in the FPGA works fine however, reading MISO always returns 0xff. If I change to SPIM1, it always returns 0x00. I have checked the output of the SPI slave using scope and signal tap and it sends the correct bytes out, it just doesn’t arrive in Linux.
I have tried different ways of accessing the SPI but they all have the same problem:

# echo \ne "\x5555" | spi-pipe -d /dev/spidev0.0 | hexdump -C
00000000  ff ff ff ff ff ff ff ff  ff ff                    |..........|

I’d appreciate any help or insight. Thanks

When you redirect SPI from FPGA-HPS-Pins throw FPGA to FPGA-Pins you need a new preloader too, because preloader controls Pinmultiplexer Function of FPGA-HPS-Pins.