Sharing onchip memory betwin FPGA and HPS


The question is about DE0-Nano-SoC (5CSEMA4U23C6). I am trying to read samples from ADC and store in onchip memory blocks in the FPGA part of the device and then read this data in a user space program in the HPS part. I desired to use LW AXI bridge.
I implemeted the design of the FPGA part, inserted IP-Core for one-port-ram into my block diagram of the device, then created the project in Qsys: inserted HPS and one-port-ram, connected they and generated design files. After it I was unsuccessful in executing TCL pin assignments script. The error was about that I don’t use the memory or something else.

Is there any explanations, sample projects or discussions which can help me to understand how it’s possible to implement the interaction betwin FPGA and HPS throught buffer in onchip memory?

I seen some topics about how to use DMA from FPGA, how to transfer data with SDRAM but I would like to use LW AXI bridge to not to build the bootloader and simplify the project as it possible. The bandwidth is not an issue.

There are a lot of information about how to implement using of PIO, SDRAM and so on but I am looking for simple data samples transfer already for a few monthes with no results. Such transfer is expected to be something very simple to implement but it seems I can’t to do it without some help from more expirienced users.

Thanks a lot for any help and sugestions.
If any additional information is requiered I am happy to provide it.