I am trying simulate f2h Ace-Lite interface in our design.
So far i see that f2h not implemented in side HPS model, it’ left unconnected.
Did some one able see transactions over this interface to SDRAM of HSP?
Thanks,
I am trying simulate f2h Ace-Lite interface in our design.
So far i see that f2h not implemented in side HPS model, it’ left unconnected.
Did some one able see transactions over this interface to SDRAM of HSP?
Thanks,