Sopc2dts crashing out with error, how to debug?

Linux Kernel
1

Hello everyone,

I’m debugging a board with Cyclone V on it and have gotten to the point where the rocketboard supplied linux kernel is falling short of my configuration. For example Ethernet needs some PHY TXCLK tweaking, and the second MAC is not detected by u-boot or linux.

I’m trying to run sopc2dts to generate a dts for my board, but it’s crashing out.

Here is the log:

java -jar ~/sopc2dts/sopc2dts.jar --input CPU_Subsys2.sopcinfo --output frank.dts --bridge-removal all --clocks -v
Component alt_xcvr_reconfig_0 of class alt_xcvr_reconfig is unknown
Component pll_0 of class altera_pll is unknown
Component wtec_smart_engine_i_light_engine_0 of class wtec_smart_engine_i_light_engine is unknown
Try to eliminate hps_bridge_avalon: hps_0_bridges_f2h
MasterIF sopc2dts.lib.components.Interface@65b3120a slaveIF null
Component pll_0 of class altera_pll is unknown
Component wtec_smart_engine_i_light_engine_0 of class wtec_smart_engine_i_light_engine is unknown
Try to eliminate hps_bridge_avalon: hps_0_bridges_f2h
MasterIF sopc2dts.lib.components.Interface@65b3120a slaveIF null
dts memory section: No memory nodes specified. Blindly adding them all
Array index out of range: 3
Exception occurred: use -v for more information
sopc2dts - rel_14.0_RC3-44-g97a55b1
Usage: sopc2dts <arguments>
Required Arguments:

I tried creating a qsys that doesn’t have any special hardware in it, but the same error message occurs. Can someone advise me on how to track this down?

I’m really hoping the tool will enable the second MAC and the PCIe port in the kernel as well as in u-boot.

2

So after a couple of days of debugging I’ve isolated the issue to the PCI module in my qsys. Specifically the Cra port of the PCI module.

Specifically, the error comes from this code:

	private void addTxsNode(Connection conn, DTNode node) {
		Vector<String> vRegNames = new Vector<String>();
		Vector<Long> vRegs = getReg((conn != null ? conn.getMasterModule() : null), vRegNames);
		int txsRegPosition;
		int width = 2;
		if (conn != null) {
			width = conn.getMasterInterface().getPrimaryWidth() + conn.getMasterInterface().getSecondaryWidth();
        }

		for(txsRegPosition=0; txsRegPosition<vRegNames.size(); txsRegPosition++) {
			if(vRegNames.get(txsRegPosition).equalsIgnoreCase("txs"))
				break;
		}
		if(vRegs.size() > 0) {
			node.addProperty(new DTProperty("ranges"));
			node.getPropertyByName("ranges").addHexValues(
					new long[] {PCI_PHYS_HI_RELOCATABLE | PCI_PHYS_HI_SPACE_MEM32, 0, 0,
							vRegs.get(txsRegPosition*width), vRegs.get(txsRegPosition*width + 1),
							0x0, vRegs.get(txsRegPosition*width + 2)});
		}
	}

The error is thrown by one of the vRegs.get() calls. The issue is that vRegs has only three entries and width is 3.

The problem I’m having now is figuring exactly what width is and how it is set and I don’t understand what the code is attempting to output.

If there’s documentation on the code, that would help a lot. If there’s an expert who has some time that would be great.

3

I think I figured it out, but I’d like some clarification. There are ports on the PCI express module which are not Txs, namely Cra. The code was not checking to ensure that the port they were documenting to the dts file was indeed a Txs. I added some code to ensure that only txs was being documented:

	private void addTxsNode(Connection conn, DTNode node) {
		Vector<String> vRegNames = new Vector<String>();
		Vector<Long> vRegs = getReg((conn != null ? conn.getMasterModule() : null), vRegNames);
		int txsRegPosition;
		int width = 2;
		if (conn != null) {
		    System.out.println("conn is not null!");
			width = conn.getMasterInterface().getPrimaryWidth() + conn.getMasterInterface().getSecondaryWidth();
        }

		for(txsRegPosition=0; txsRegPosition<vRegNames.size(); txsRegPosition++) {
			if(vRegNames.get(txsRegPosition).equalsIgnoreCase("txs"))
				break;
		}
		if (txsRegPosition < vRegNames.size()) {
            if(vRegs.size() > 0) {
                node.addProperty(new DTProperty("ranges"));
                node.getPropertyByName("ranges").addHexValues(
                        new long[] {PCI_PHYS_HI_RELOCATABLE | PCI_PHYS_HI_SPACE_MEM32, 0, 0,
                                vRegs.get(txsRegPosition*width), vRegs.get(txsRegPosition*width + 1),
                                0x0, vRegs.get(txsRegPosition*width + 2)});
            }
		}
	}
4

Here is a patch file:

--- sopc2dts_orig/sopc2dts/lib/components/altera/PCIeRootPort.java      2021-01-14 09:15:30.685238452 -0800
+++ sopc2dts/sopc2dts/lib/components/altera/PCIeRootPort.java   2021-01-14 09:21:25.073667449 -0800
@@ -96,13 +96,14 @@
                        if(vRegNames.get(txsRegPosition).equalsIgnoreCase("txs"))
                                break;
                }
-
-               if(vRegs.size() > 0) {
+               if (txsRegPosition < vRegNames.size()) {
+                       if(vRegs.size() > 0) {
                        node.addProperty(new DTProperty("ranges"));
                        node.getPropertyByName("ranges").addHexValues(
-                                       new long[] {PCI_PHYS_HI_RELOCATABLE | PCI_PHYS_HI_SPACE_MEM32, 0, 0,
-                                                       vRegs.get(txsRegPosition*width), vRegs.get(txsRegPosition*width + 1),
-                                                       0x0, vRegs.get(txsRegPosition*width + 2)});
+                               new long[] {PCI_PHYS_HI_RELOCATABLE | PCI_PHYS_HI_SPACE_MEM32, 0, 0,
+                               vRegs.get(txsRegPosition*width), vRegs.get(txsRegPosition*width + 1),
+                               0x0, vRegs.get(txsRegPosition*width + 2)});
+                       }
                }
        }