Stratix 10 fpga2sdram

I’m trying to access SDRAM on HPS from the Stratix 10 FPGA.

First I tried to connect through f2h_axi_slave, but the FPGA would always read 0 on the bus.
I use dma_alloc_coherent and use the handle as address when accessing the bus from the FPGA.

I suspect that I might have to set up the FPGA Translation Buffer Unit correctly but I do not know how.

So I tried a different approach:
use the fpga2sdram bridge. In this case the read never completes (there is no readdatavalid).
I tried settings up the firewall:
I checked brgmodrst which was correctly set to 0.
But nothing helped…

Has anyone achieved fpga2hps / fpga2sdram on the stratix 10 and knows what I might be missing?

Thank you!

Intel support pointed me to this:

I did not setup the sidebandmanager.

Now that I added the script to u-boot it works.