Stratix 10 SOC Dev Board - Signal Tap Not Working

I have a Stratix 10 Soc Development kit and it is booting with HPS first with the root file system on the SD card. The Core rbf is being loaded with uboot using fatload… fpga load… and then boot. I can interact with the memory mapped space with the hardware at expected addresses from the HPS, so I think the core rbf loaded correctly. When trying to use signal tap, I can see the FPGA in the JTAG chain but it always tells me Program the device to continue. I know this is the stp file that corresponds with this compile, so I am not sure what is wrong. Typically when I have seen this on other boards, its because I have chosen the wrong stp file or somehow corrupted it.

Here is my selected jtag device.

There are two devices in the device list and I have tried both of them.

This design is based on the 2020.05 GSRD and the was built with the instructions in Stratix 10 SoC GSRD with the HPS first linux patch from Stratix 10 SoC HPS First Single QSPI Flash Boot

Quartus version: 20.1

Any Ideas are appreciated. Thanks!

Have you solved it? I meet the same issue , everything seems ok except the SignalTap.
By the way. My boot setting is FPGA first.

I have not found a solution, but it is a good data point to know that someone is having a problem with a different boot process. Are you using an SOF to load the FPGA? What version of Quartus are you using?

I am using version 19.4 and I have been able to use the signal taps without many issues. One thing to try is to reduce the clock frequency from 24Mhz to 16Mhz. That seems to help with detecting the signal taps. You will also want to use it with the signal tap analyzer window. I will usually run generate ip, then synthesis, then you should be able to add nodes in the signal tap logic analyzer window for the nets. Once you have added the nodes, runt he whol compilation. I have not gotten the rapid recompilation to work.

Thanks! That seems to have worked on 20.1.