SystemBuilder for DE10Nano

If HPS is selected a QSF file is generated for the pin mapping. Why the DDR pins not mapped to a PIN?

For example
set_instance_assignment -name IO_STANDARD “SSTL-15 Class I” -to HPS_DDR3_ADDR[0]
HPS_DDR3_ADDR is not assigned to a pin.

So, when trying to create a HPS, verilog generates errors because there is not a true ping mapping.
If you look at some other qsf files that say system builder generated it has additional info…
set_instance_assignment -name IO_STANDARD “SSTL-15 CLASS I” -to HPS_DDR3_ADDR[0] -tag __hps_sdram_p0

What I’m doing wrong?