TERASIC NANO/ATLAS DE0 SOC KIT, my_first_hps-fpga tutorial an bdf schematic file

Hello, in this example controlling LEDS throught AXI from C code,
the project in QUARTUS II in top level ghrd.v shows this “connection” (from qsys export) as:
soc_system u0 (

and LED bus deffinition on MODULE at ghrd.v, (assigned to LED pins in PIN PLANNER)
output [7:0] LED,

then if i create this BUS:
output [7:0] DATA1,

and change the line in SOC_SYSTEM:
soc_system u0 (

Compiler shows like PIN LED[x] is stuck at GND, dowsnt work (BDF schematic file does not affect in the project).

If i put DBF as TOP LEVEL in hierarchy and create a symbol for ghrd.v, then connecting to pins out (like an “Interface” of the original example) like:

In schematic view, generated symbol HPS (system_soc) DATA1 OUT port connected to PINS (LEDS) through a BUS.

y get errors and doesn’t work.

How can i use a DBF schematic in a project with SYSTEM_SOC module as shows my_first_hps-fpga example?

Check the pin assignments!

Hi, finally i fix it:
Instead create and use top level verilog symbol file (where hps instance is, bus and ports definition), i generate it through QSYS, checking “create symbol” before GENERATE button.
Then removing top level verilog from project. Creating schematic view at top level and adding new QSYS SOC symbol.
At this moment no pin assignments are created for HPS peripherals, manually i connect each port from System SOC symbol instance to corresponding signal (defined at pin planner) using old verilog top level file as guideline,
Adding some extra modules (also defined in verilog file) and connecting PIO_LED to correspondind LED pin finally i get it working as scheme “project mode”. All pin assignments from HPS (sdram, etc) peripherals are created at fitter time.