Timing Analysis for HPS-FPGA design

I’ve been playing around with designing parallel multipliers in Verilog at the gate level by making use of Carry Save Adders. I then pass inputs from the HPS into my FPGA and vice-versa via the lightweight bridge. Right now I am confused with doing timing analysis for my design.

I’ve read about setup and hold slacks, data arrival time and data required time. But since my design does not have any sequential elements such as flip-flops, how can we get started with measuring timing for the design? My Verilog module does not take any clock elements as input.

I would want to find out the clock frequency at which my design can run at, and also, if possible, do some performance comparison between my design and a normal serial multiplier.

Any help is greatly appreciated! :slight_smile:

I’m using a DE1-SoC board with a Cyclone V chip.