U-Boot 2013.01 and support for Macronix MX66L2G45G

eldorr · January 27, 2022, 1:47pm

Hi!

I am looking into the possibility for replacing our 256MByte QSPI Flash type Micron MT25QL02 with a similar size MX66L2G45G from Macronix. The U-Boot version I am running is rather old … 2013.01 from Rocketboard, with various modifications based on our needs.

I have done what I consider the necessary adaptions to enable detection of the MX66L2G45G, but SPL does not “see” a valid U-Boot where - in the the MT25QL02 case - everything works smooth.

Attaching some DEBUG output here:
U-Boot SPL (QSPI CS#0) 2013.01.01-KS800 (Jan 27 2022 - 15:14:27)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 700 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 350000 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers

… then a lot of SDRAM-stuff…before finally

INFO: DMA BASE Address = 0xffe01000
SDRAM: ECC initialized successfully with 7995 ms
Setup interrupt controller… IRQ SP at 0x00000000 with size 0x00000400
SDRAM: ECC Enabled
boot device - 2
spi_setup_slave: bus 0 cs 0 max_hz 50MHz mode 3
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 350000000Hz sclk 50000000Hz Div 0x3
cadence_qspi_apb_config_baudrate_div: ref_clk 350000000Hz sclk 1000000Hz Div 0xf
cadence_qspi_apb_config_baudrate_div: ref_clk 350000000Hz sclk 50000000Hz Div 0x3
SF: Read data capture delay calibrated to 3 (0 - 6)
SF: Got idcodes
SF: Detected MX66L2G45G with page size 65536, total: 268435456
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 350000000Hz sclk 50000000Hz Div 0x3
mkimage signature not found - ih_magic = ffffffff
spi_claim_bus: bus:0 cs:0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 350000000Hz sclk 50000000Hz Div 0x3
Jumping to U-Boot
Bad image with no CRC. Image possibly erased

ERROR ### Please RESET the board

Obviously; “mkimage signature not found - ih_magic = ffffffff” but unsure why it cant be read/found.

Any hints and tips are appreciated.

Thanks.

/Eldor

claudio · August 17, 2023, 8:43pm

Hi Eldor,
Did you resolve this issue with Macronix flash? I have an issue as well with replacing Micron with Macronix flash. In the SPL, U-boot CRC checksum fails with a different checksum read every time. The flash read appears to fail.and I get the same error: ERROR #### Please RESET the board
Thanks. Regards Claudio

eldorr · August 18, 2023, 6:13am

Hi!
A long time ago this, but I believe that the below patch was the remedy in my case.
Good luck!
/Eldor

… here goes
diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c
index c97a39d…da48557 100644
— a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -77,8 +77,82 @@ static const struct macronix_spi_flash_params macronix_spi_flash_table[] = {
.nr_blocks = 256,
.name = “MX25L12855E”,
},

{
```
  .idcode = 0x201c,
```
```
  .nr_blocks = 4096,
```
```
  .name = "MX66L2G45G",
```
},
};

+#define BIT(nr) (1UL << (nr))
+#define SR_QUAD_EN_MX BIT(6)
+#define CMD_READ_STATUS 0x05
+/**

- macronix_quad_enable() - set QE bit in Status Register.
- @nor: pointer to a ‘struct spi_nor’
- Set the Quad Enable (QE) bit in the Status Register.
- bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
- Return: 0 on success, -errno otherwise.
*/
+static int macronix_quad_enable(struct spi_flash *flash)
+{
struct spi_slave *spi = flash->spi;
u8 cmd, val;
int ret;
cmd = CMD_READ_STATUS;
ret = spi_flash_cmd_read(spi, &cmd, 1, &val, 1);
if (ret) {

  debug("SF: Failed to read status register\n");

```
  return ret;
```
}
if (val & SR_QUAD_EN_MX)
```
  return 0;
```
val |= SR_QUAD_EN_MX;
return spi_flash_cmd_write_status(flash, val);
+}

+#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode /
+#define SPINOR_OP_EX4B 0xe9 / Exit 4-byte mode */
+static int macronix_set_4byte(struct spi_flash *flash, u8 enable)
+{

u8 cmd;
int ret;
ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {

  debug("SF: enabling write failed\n");

```
  return ret;
```
}
cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
ret = spi_flash_cmd_write(flash->spi, &cmd, sizeof(cmd), NULL, 0);
if (ret) {

  debug("SF: fail to %s 4-byte address mode\n", enable ? "enter" : "exit");

```
  return ret;
```
}
ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret < 0) {

  debug("SF: write status register timed out\n");

```
  return ret;
```
}
return 0;
+}

+int macronix_wait_flag_status_ready(struct spi_flash *flash)
+{

return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+}

struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
{
const struct macronix_spi_flash_params *params;
@@ -98,6 +172,7 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
}

flash = malloc(sizeof(*flash));

memset(flash, 0, sizeof(struct spi_flash));
if (!flash) {
debug(“SF: Failed to allocate memory\n”);
return NULL;
@@ -113,8 +188,16 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
flash->sector_size = 256 * 16 * 16;
flash->size = flash->sector_size * params->nr_blocks;

/* Clear BP# bits for read-only flash */
spi_flash_cmd_write_status(flash, 0);

/* Wait / Ready / Erase timeout */
flash->poll_read_status = macronix_wait_flag_status_ready;
/* Quad enable */
debug(“SF: Macronix : QUAD Enable\n”);
macronix_quad_enable(flash);
/* 4-byte enable */
debug(“SF: Macronix : 4-byte Enable\n”);
macronix_set_4byte(flash, 1);

return flash;
}
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 9416c30…65b99a7 100644
— a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -540,6 +540,7 @@
#define CONFIG_SPI_FLASH /* SPI flash subsystem /
#define CONFIG_SPI_FLASH_STMICRO / Micron/Numonyx flash /
#define CONFIG_SPI_FLASH_SPANSION / Spansion flash /
+#define CONFIG_SPI_FLASH_MACRONIX / Macronix flash /
#define CONFIG_CMD_SF / Serial flash commands /
/ Flash device info */
#define CONFIG_SF_DEFAULT_SPEED (50000000)

eldorr · August 18, 2023, 6:13am

Uhhh … the formatting messed up the patch If you have an e-mail address I can send the patch directly to you.
/Eldor

claudio · August 21, 2023, 9:03pm

you can also use email: claudiospinelli123@yahoo.com Thanks.