Using a 128bit HPS2FPGA-Bridge with a kernel module

I’m trying to write a linux kernel module utilizing a 128-bit AXI bridge from HPS to the FPGA. Using the iowrite/ioread functions, only 32bits of data get transferred at once. I found the alt_read_word/alt_write_word macros in the socal.h, are those appropiate for this usecase? Is there any documentation available for that library, maybe an example design?

Any other way I might achieve this? Thanks in advance!

Cortex A9 maximum data size ir 64 bits. Bus connecting uP and L3 is also 64 bits.

But I can configure the HPS-to-FPGA-Brdige to be 128bits wide. I assumed there was some logic combining data words or anything similar?

@Brillow Yeah. I was thinking you were trying to transfer 128bits from program with one instruction, that is not possible. One reason is that you can only define 64bit variables in Cortex A9. I pointed that because it is maybe your problem (a programming problem).

Of course, you can use HPS-FPGA bridge in 128 bits even when you are connecting 32bit peripherals to it. Qsys puts the logic in order to perform the address map you see in Qsys. In fact transfers are faster in 128 bits mode than the others.

Personally I always use memcpy function from std library to move data because it optimizes transfers depending on data size and takes into account that issues (uP is 32bits but bus to L3 64bits, takes into account AXI protocol to optimize time (AXI is the internal bus that connects everything UP, L1,L2,L3). It is better than manually moving data using pointers and for loops. The drawback for a driver is the function overhead. So maybe you can dig in the .c file where memcpy is written, try to understand it and find what kind of basic operations it is using.

When uP does access to memory or peripherals it does it doing access petitions to L1 and it does it using 32bits. It is L1 or L2 who can pack some petitions and do 64bit petitions and use the streaming capabilities of AXI to get transfers done faster. You can check CycloneV Handbook, ARMv7-A-R_architecture_reference_manual and Cortex-A9 revr3p0 Technical Ref Manual

@roberbot Thanks so much for your help, I will definitely search the documentation to find out more. I am using memcpy right now, but it is only using 32-bit transfers into the FPGA and does not seem to combine them to fill the 128bits of the HPS2FPGA-bridge. Do I have to adjust something in the GPV to make that work?