Using external JTAG debugger with Intel Stratix 10 SX Dev Kit for HPS debugging


I am trying to carry out HPS Cortex-A53 debugging via external JTAG debugger (Arm DSTREAM), and ARM development studio however the debugger is not able to locate any devices on the JTAG chain when connected via the Mictor-38 JTAG on the HPS JTAG on HPS IO-48 OOBE Daughter Card or the external J1 JTAG header connector.

My board is running the default GHRD and SPL and boots fine onto U-Boot:

U-Boot SPL 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)
Reset state: Cold
MPU 1000000 kHz
L3 main 400000 kHz
Main VCO 2000000 kHz
Per VCO 2000000 kHz
EOSC1 25000 kHz
HPS MMC 50000 kHz
UART 100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1105 ms
QSPI: Reference clock at 400000000 Hz
WDT: Not found!
Trying to boot from MMC1

U-Boot 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)socfpga_stratix10, Build: jenkins-uboot-socfpga-AXIS_1=s10,AXIS_2=v2019.10,AXIS_3=atgit-326

CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
MMC: dwmmc0@ff808000: 0
Loading Environment from MMC… *** Warning - bad CRC, using default environment

At the moment by board is running a GSRD image from QSPI from and the board successfully boots into U-Boot however JTAG connection fails.

I need help to understand if the FPGA design needs to be updated to make HPS JTAG visible to the Mictor-38 connector or is it something that is by default available and should work. I am using off, off, on, on , on ,on , on, on configuration for the SW1 JTAG selection switch.

jtagconfig via the onboard Intel FPGA cable does show that HPS is indeed present on the scan chain:


  1. Stratix 10L SoC Dev Kit [1-2]
    C321D0DD 1SX280LH(2|3)/1SX280LN2(|AS)/…


Any help here in this regard ?