Using the OpenOCD with cyclone v

1

hello,

Someone already use the Cyclone V with the OpenOCD?
I’m developing with the helio board and want debug the ARM with the openocd + gdb.
Someone has some tips?

Thanks

2

Hi!!
I can just give you the first step! (check if your JTAG cable is supported)

//Download from sourceforge
tar -vxf openocd-0.9.0-rc1.tar.bz2

cd openocd-0.9.0-rc1

// Take a look at ./configure --help
./configure --enable-usb-blaster-2

// If you get a libusb-1.x error
sudo apt-get install libusb-1.0.0-dev

make
sudo make install

bye

3

I hava the usb-blaster of terasic and the usb-blaster of the altera. Do you know which one works?

Thanks for reply

4

I’m having a problem with the chain. Do you put the FPGA and the ARM in the chain or only the ARM?

Thanks.

5

HI!!
the altera usb blaster should work fine
http://openocd.org/doc/html/Debug-Adapter-Hardware.html#Debug-Adapter-Hardware
And yes!! Both HPS(ARM) and FPGA are in one chain. First the HPS and then the FPGA!
take a look at
…/openocd-0.9.0-rc1/tcl/board/altera_sockit.cfg
…/openocd-0.9.0-rc1/tcl/interface/altera-usb-blaster.cfg
…/openocd-0.9.0-rc1/tcl/interface/altera-usb-blaster2.cfg
…/openocd-0.9.0-rc1/tcl/target/altera_fpgasoc.cfg
bye

6

I’m having the following error:

willianhenrique@willian-Z230:~/workspace/openocd-0.9.0-rc1$ ./bin/openocd -s share/openocd/scripts -f interface/altera-usb-blaster2.cfg board/altera_sockit.cfg
Open On-Chip Debugger 0.9.0-rc1 (2015-11-26-15:41)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Warn : Adapter driver ‘usb_blaster’ did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag’
Info : Altera USB-Blaster II found (Firm. rev. = 1.27)
Info : This adapter doesn’t support configurable speed
Warn : There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
Info : JTAG tap: auto0.tap tap/device found: 0x02d020dd (mfg: 0x06e, part: 0x2d02, ver: 0x0)
Info : JTAG tap: auto1.tap tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x02d020dd"
Warn : AUTO auto1.tap - use “jtag newtap auto1 tap -irlen 2 -expected-id 0x4ba00477”

Error: IR capture error at bit 4, saw 0x03FFFFFFFFFFFFFFFFFFFFFFFFFFC555 not 0x...3

Warn : Bypassing JTAG setup events due to errors Warn : gdb services need one or more targets defined

Do you know why?
I can’t use the usb-blaster in my PC don’t work, it break the openocd, I don’t know why.
I’m using the blaster 2 that came in board of helio board.

Thanks

7

Hi!
I dont know the daisy chain in the helios board! Can you please type:
jtagconfig (using the byteblaster II)

You have to modify the cfg files!! I can tell you how to do it!! but I need the chain!
bye

8

Hi everybody!!
I’am also having problems with openocd!! (Altera SoC development kit - ByteblasterII)

ERROR
"
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
"

COMMAND
openocd -f tcl/interface/altera-usb-blaster2.cfg -f tcl/board/altera_board_soc_dev_kit.cfg

altera-usb-blaster2.cfg (…/interface)
interface usb_blaster
usb_blaster_device_desc "USB-Blaster II"
usb_blaster_vid_pid 0x09fb 0x6010 0x09fb 0x6810
usb_blaster_lowlevel_driver ublast2
usb_blaster_firmware …/altera/14.1/quartus/linux64/blaster_6810.hex

altera_board_soc_dev_kit.cfg (…/board)
source …/tcl/target/altera_soc_dev_kit.cfg

altera_soc_dev_kit.cfg (…/target)
set _CHIPNAME fpgasoc

jtag newtap $_CHIPNAME.maxv tap -irlen 10 -ircapture 0x1 -irmask 0x3 -expected-id 0x020a40dd
jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x1 -irmask 0x3 -expected-id 0x02d020dd
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477

set _TARGETNAME1 $_CHIPNAME.cpu.0

target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x80110000

$_TARGETNAME1 configure -event reset-start { adapter__khz 1000 }
$_TARGETNAME1 configure -event reset-assert-post “cortex__a dbginit”
$_TARGETNAME1 configure -event gdb-attach { halt }

Ideas???
bye

9

HI!!!
This works fine with the USB Blaster!

use:
openocd -f tcl/interface/altera-usb-blaster.cfg -f tcl/target/my.cfg

FILE:
tcl/target/my.cfg

 ##########################################
  # Altera Cyclone V
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME fpgasoc
}


# Subsidiary TAP: fpga (tap)
if { [info exists FPGA_TAPID] } {
   set _FPGA_TAPID $FPGA_TAPID
} else {
   set _FPGA_TAPID 0x02d020dd
}
jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID


# CoreSight Debug Access Port (dap HPS)
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID



#
# Cortex-A9 target
#

# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0  -  0x80110000
# core 1  -  0x80112000

# Slow speed to be sure it will work
adapter_khz 1000

set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1

# A9 core 0
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x80110000

$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
$_TARGETNAME1 configure -event gdb-attach { halt }


# A9 core 1
target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x80112000

$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
$_TARGETNAME2 configure -event gdb-attach { halt }


#target smp $_TARGETNAME1 $_TARGETNAME2


proc cycv_dbginit {target} {
        # General Cortex-A8/A9 debug initialisation
        cortex_a dbginit
}

 ###################################

This works only for this daisy chain TDI -> ARM(hps) -> ALTERA(fpga) -> TDO
If you have TDI -> ALTERA(fpga) -> ARM(hps) -> TDO, switch the “jtag newtap” definitions. First the hps and then the fpga.

10

Did you succeed to halt CPU.1 ?
I got timeout.

I can halt CPU.0, but I can’t halt CPU.0

As for -dbgbase, I think we don’t need because openocd automatically
read them from dap rom. But you may put them.

However according altera hps memory map document, they are 0xFF110000 and 0xFF112000. But openocd automatic detection said they are 0x80110000 and 0x80112000. And for sure, openocd works well on the later parameters.

strange.

11

Hi guys,

I use a DE1-SoC board with a cyclone V SoC.

I tried to get openocd working. I use the altera-usb-blaster2.cfg file with adapted firmware path and the target config posted by murillo. I checked the jtag chain.

First it seems that my FPGA has another id:
Warn : JTAG tap: fpgasoc.fpga.tap UNEXPECTED: 0x02d120dd (mfg: 0x06e, part: 0x2d12, ver: 0x0)
Error: JTAG tap: fpgasoc.fpga.tap expected 1 of 1: 0x02d020dd (mfg: 0x06e, part: 0x2d02, ver: 0x0)

It seems to be 0x02d120dd instead of 0x02d020dd.

However, there’s a much bigger problem. I get following error:
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0

As far as I found out the blaster uses a clock that is too high. It seems that openocd is not able to switch the clock frequency down.

is there any solution for this yet?

Thank you