What is the address of 0x100000000?


Hi all,

I am trying some GPIO stuff on my soc board, and I found:

root@cyclone5:/sys/class/gpio# ls -l
total 0
–w------- 1 root root 4096 Jan 1 1970 export
lrwxrwxrwx 1 root root 0 Sep 1 14:32 gpiochip161 -> …/…/devices/virtual/gpio/gpiochip161
lrwxrwxrwx 1 root root 0 Sep 1 14:32 gpiochip165 -> …/…/devices/virtual/gpio/gpiochip165
lrwxrwxrwx 1 root root 0 Sep 1 14:32 gpiochip169 -> …/…/devices/virtual/gpio/gpiochip169
lrwxrwxrwx 1 root root 0 Jan 1 1970 gpiochip171 -> …/…/devices/sopc.0/ff70a000.gpio/gpio/gpiochip171
lrwxrwxrwx 1 root root 0 Jan 1 1970 gpiochip198 -> …/…/devices/sopc.0/ff709000.gpio/gpio/gpiochip198
lrwxrwxrwx 1 root root 0 Jan 1 1970 gpiochip227 -> …/…/devices/sopc.0/ff708000.gpio/gpio/gpiochip227
–w------- 1 root root 4096 Jan 1 1970 unexport
root@cyclone5:/sys/class/gpio# cd gpiochip161
root@cyclone5:/sys/class/gpio# ls
export gpiochip161 gpiochip165 gpiochip169 gpiochip171 gpiochip198 gpiochip227 unexport
root@cyclone5:/sys/class/gpio# cd gpiochip161
root@cyclone5:/sys/class/gpio/gpiochip161# ls
base label ngpio power subsystem uevent
root@cyclone5:/sys/class/gpio/gpiochip161# cat label

I am fine with the GPIO under HPS, but confused with the ones under FPGA:
I know the address 0x00010040 is assigned in Qsys for FPGA component, and where does the address
0x1 0000 0000 come from, and why is this value?

According to this document:

in Part 6, Section 1, it says:
"1. Go to Lightweight HPS2FPGA Address Map and write down the address offsets for the DIP switches and the buttons, and add the offset of the LW_H2F bridge of 0x100000000 "

But in the “Lightweight HPS2FPGA Address Map” it says:
“The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table.”

How to understand this?

Thanks so much~~


I forget to upload the address map in qsys…


The 0x1_0000_0000 is really not an address (kind of… it is an address offset with an index into the bridge number, but I’ve tried to explain below). There are ranges defined in the device tree for each soft IP core connected to the H2F and LW_H2F bridges. Here is an example device tree source snippet:

	       ranges = <0x00000000 0x00400000 0xc0400000 0x00040000>,
			<0x00000000 0x10000000 0xd0000000 0x10000000>,
			<0x00000001 0x00004000 0xff204000 0x00004000>,
			<0x00000001 0x00000000 0xff200000 0x00000100>,
			<0x00000001 0x00000130 0xff200130 0x00000008>,
			<0x00000001 0x00000120 0xff200120 0x00000010>,
			<0x00000001 0x00000110 0xff200110 0x00000010>,
			<0x00000001 0x00000100 0xff200100 0x00000010>;

The first 32bit value (on each line) is the bridge the IP is connected to: 0x00000000 is the H2F bridge and 0x00000001 is the LW_H2F.

The second 32bit value is the address offset from that bridge base address.

The third 32bit value is the address of that IP as seen by the Cortex-A9.

The fourth 32bit value is the size of the address space in bytes.

For example, the led_pio in your address map above would most likely show with the following ranges:

<0x00000001 0x00010040 0xff210040 0x00000010>,

The onchip ram in your example would show with these ranges settings:

<0x00000000 0x00000000 0xc0000000 0x00010000>,

The first two 32bit values concatenated together yields the numbers you’ve mentioned.

I hope this helps!


I’m struggeling with a problem with my minimal design using a pio and an uart only connected to the LW Hps2fpga.

Details of my system on alteraforum
Can i see somewhere in the linux if the ranges are correctly recognized by linux and the MMU programmed properly? Because im almost certain my design is correct, bridge handoff done properly etc. But as soon as i try to write to my mmapped() Pio the kernel just hangs.

I use a custom devicetree as the soc2fpga isnt working that great. I want to know if the kernel knows about my address space living behind the bridge


the device tree is in /proc folder
I did the example comming in the DE1-SoC documentation (called my first-hps-fpga) and it properly access FPGA peripheral using mmap. You can start from there.
Here I do mmap a memory in the address 0x00000000 of the HPS-FPGA bridge (Address 0xC0000000 for processor). You can take it as another example: