Why does jtag to FPGA called "non-secured"?


I am trying to understand the usage of secured/non-secured terminology in JTAG.
I see it in being mentioned in diagram here:

Does anyone knows ?

Thank you,

ARM has 2 separate buses for some peripherals. A secure one and a non-secure one. I dont understand quite well but basically they provide two buses for each of those peripherals, with different degrees of security regarding access. In practice this makes that each peripheral can be accessed by 2 different base address in address space.This peripherals use double memory in the address space.