I’m struggling with SDRAM access over a 128bit AXI F2SDRAM port on my Cyclone 5 DE10 Nano board.
On the FPGA, my IP core tries to access address 0x30100000. That’s the address I get from my device driver (dma_alloc_coherent). The controller accepts the read request but the response is a repeated byte pattern, e.g. 0xb2b2b2b2b2b2b2b2b2…
I tried to move CMA region to a lower address (0x1c000000) with the same result. Surprisingly, other addresses can be read from FPGA. I guess, the problem is caused by some Linux settings/actions.
What is even more weird: Reading the memory at 0x30100000 (resp. 0x1c000000) with CPU reveals that it is filled with random garbage. After access via FPGA, a region of 1 MB starting at address 0x30100000 is suddenly filled with the byte pattern I read on the FPGA SDRAM port.
Read access looks OK in signal tap:
Any ideas what is causing this? Probably any cache effects?