Enable FPGA-to-HPS SDRAM Interface

How can you enable the FPGASDRAM interface from the newer version of u-boot that includes the preloader?

There is what seems to be an older guide here (https://rocketboards.org/foswiki/Documentation/GSRD131ProgrammingFPGA) on using a u-boot command

run bridge_enable_handoff

This command is not in the environment in the newer releases of u-boot-socfgpa. I am using the branch origin/socfpga_v2019.04

I am fairly confident this bridge is not enabled based on what I am seeing in sysfs in Linux

root@cyclone5:~# ls /sys/class/fpga_bridge/
br0 br1
root@cyclone5:~# cat /sys/class/fpga_bridge/br0/name
root@cyclone5:~# cat /sys/class/fpga_bridge/br1/name

The question follows the issues I was seeing from SignalTap when debugging the master ports to a Altera DMA core mentioned in my recent post (Cyclone 5 F2SDRAM issue)

It seams that the command was replaced with the following one:

bridge enable

Not sure how it works on the CV device but at least on the A10 devices the bridges should be declared in the u-boot device tree blob.

I do run that command in my script with a bit mask of 0xffffffff. The interface does not seem to be enabled.

bridge enable 0xffffffff

Where is the uboot device tree blob files located? In u-boot-socfpga source or linux-socfpga? Is it the same blob that is used for the kernel? Where are the files for Arria10? Did you have to change anything in those files?

Where can I find an example of the FPGA2HPS SDRAM node for the device tree? The other interfaces are listed in the decompiled dts I am looking at, but not the node for FPGA2HPS. I think I might need to add it manually.