Missing /dev/fpga0 device on DE0-nano-SoC


I’ve just compiled the Linux 4.1 LTSI kernel and Poky. I’m able to boot the kernel on my DE0-nano-SoC board, using the default device tree that comes with the kernel. dmesg seems fine so far, no errors. Though /dev/fpga0 is missing.

I can also see successfull registering of the Altera FPGA Manager driver:

Jun 21 14:44:32 cyclone5 kernel: [ 1.985422] fpga_manager fpga0: Altera SOCFPGA FPGA Manager registered
Jun 21 14:44:32 cyclone5 kernel: [ 1.992306] altera_hps2fpga_bridge ff400000.fpga_bridge: fpga bridge [lwhps2fpga] registered
Jun 21 14:44:32 cyclone5 kernel: [ 2.022307] altera_hps2fpga_bridge ff500000.fpga_bridge: fpga bridge [hps2fpga] registered
Jun 21 14:44:32 cyclone5 kernel: [ 2.030919] fpga-region soc:base_fpga_region: FPGA Region probed

According to the driver code in “drivers/fpga/fpga-mgr.c”, the device is registered immediately before “Altera SOCFPGA FPGA Manager registered” is printed out. So it seems that the registering process was successfull.

Did anyone else see this behavior with the 4.1 LTSI kernel? Any ideas what is causing this?

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I solved the issue myself. The approach to use Device Trees and programming the FPGA under Linux has changed fundamentally. There is no /dev/fpga0 device anymore.

Instead, Linux uses Device Tree Overlays now. See the WS2 Linux Kernel Introdution lab for examples.

The Device Tree Overlay as well as the FPGA RBF file have to reside in /lib/firmware. To load the overlay, mount the configfs filesystem and create a new directory in the overlay subfolder:

mkdir /config
mount -t configfs configfs /config
mkdir /config/device-tree/overlays/test

Then write the name of your Device Tree Overlay file to a file with name “path”:

echo overlay.dtb > /config/device-tree/overlays/test/path

The kernel driver will then look for the file in “/lib/firmware” and load it into the default device tree, that came with the kernel.

If you want to load a RBF file into the FPGA, you have to replace external-fpga-config; with firmware-name = “socfpga.rbf”; in the example overlay file from the WS2 lab.

Unable to program Arria 10 FPGA from HPS Linux

How do you create the overlays from the hardware design?


I used the output of the sopc2dts tool as a hint and manually built an overlay for the fpga_base_region.
You can have a look at “Documentation/devicetree/bindings” in the Altera Linux Kernel for information on how to add some of the Altera specific IP cores to a device tree. Just grep for “altr”.
Documentation/devicetree/bindings/fpga/fpga-region.txt gives some information about the fpga_region device tree node.


Thanks for the info. It seems like using the device tree overlays is more of a development cycle flow rather than a long term release flow. When I have a release, it seems the fpga image should be stored in flash and loaded at boot (u-boot doesn’t seem to boot if a valid fpga image is not available). But when I am developing, I can use the overlays to load the fpga without having to save it off to flash and rebooting.


Another question: When I convert the .sof to .rbf, I get 2 rbfs: core and peripheral. Were you able to program the core.rbf image using overlays?


I received a single RBF file using the following command line:

quartus_cpf -c altera_atlas_soc.sof socfpga.rbf