Thanks for your reply. I have been working this for a while and tried several approaches (most likely replacing my errors with different errors and not making progress). I have tried working from the gsrd backwards, and tried working forwards with my own program (several different small test versions).
I tried your suggestion of dropping my .rbf file into a gsrd configuration. I had tried this before and did not find sucess in completing a boot and it is the same today. The .rbf file will load but that is as far as it goes. I wouldnt expect much more than that from a mixed “uboot & .RBF file” configuration. I have been able to get past (at least a little farther) the uboot lock up I was seeing earlier.
On my ‘smallest posible footprint’ version it was so pared down that there was no emif interface on the HPS so Qsys did not produce an emif.xml file. Since bsp-editor will not run without an emif.xml and a hps.xml that was a step too far back. I did try dropping in an emif.xml form the gsrd to see if the uboot produced by bsp-editor would go a little farther, and it id - my .rbf file would load and give me the ‘Full Configuration Completed’ message but it would hang after that (I suppose hanging on the SDRAM calibration and check of the emif that was not present in my Qsys).
I started working backwards from a copy of gsrd, paring off parts that I dont need or want (and particularly the parts that I cant compile since I dont have all of the IP library). In this I dropped much of the design to eliminate the partial reconfiguration, the display port, buttons, switches, leds, trace monitors, etc. This did compile and allowed a uboot to be created (via the usual process) and boots a little farther. In this the boot loads my test .rbf file acnowledges the emif interrupt a few trimes then fails the DDRCAL. Since I didnt intentionally alter the SDRAM in Qsys I didnt see why this should occur. I examined the emif.xml file from my pared down project and the one from the gsrd and they are the same.
I tried loading my program (named TestVer.rbf below) and it boots as shown below;
U-Boot 2014.10-00320-g077e579-dirty (Apr 16 2017 - 22:35:05)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
FPGA: writing TestVer.rbf …
FPGA: Early Release Succeeded.
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
Error: Could Not Calibrate SDRAM
DDRCAL: Failed
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
DRAM : 0 Bytes
data abort
pc : [] lr : []
sp : ffe3fff0 ip : 00000016 fp : 00000001
r10: ffd02078 r9 : ffe38ee8 r8 : ffe00000
r7 : ffe20450 r6 : 00000000 r5 : 00000000 r4 : ffeff000
r3 : ffe38faf r2 : ffe40000 r1 : ffe3b000 r0 : ffe38ee8
Flags: nzcv IRQs on FIQs on Mode SVC_32
Resetting CPU …
resetting …
(and then it repeats ad infinitum …)
I beleive the problem is in the uboot file and was about to start experimenting with the command line bsp tools (instead of relying on bsp-editor). I will take some time to try to understand all of the entries in the emif.xml file to see if something odd sticks out. I could have a configuration issue in Qsys and will look into that as well (I did make a lot of changes in reducing the configuration so this is a good place to start).
I am using Quartus ver 17.0 and Angstrom v2015.12. I had very good luck working with the Cyclone V (Terasic DE-1) board and proved in the concept for my project, then switched to the Arria 10, which turned out to be a bigger change than expected. I am working on getting a flat file FPGA design (as opposed to a partial reconfiguration design) working to be compatible with an IP package for USB 3.1 gen 2 that I plan to use (they use a flat file design in the code they distribute and Quartus v17.0). There seems to be a dearth of flat file examples using the HPS processors for the A10 SoC board. My project uses the HPS processors heavily which simplifies the code for the light work and keeps the FPGA free for what its best at, so you would think I am on the easy street, if only I can get a file to load.